DAC 2011 - ACC tutorials

If you plan to attend DAC 2011 (6-9 June) and are seeking solutions to minimize the impact of process, voltage, and temperature variability, improve IC performance, and reduce IC power consumption, then we suggest you visit the Tiempo booth to learn more about clockless/asynchronous chip design.

In our booth, we will present hardware demos of clockless chips in action (e.g. Contactless payment transaction application, and our TAM16 microcontroller with "continuously-variable-speed-control").

In our suite, we will present free tutorials on how to do clockless/asynchronous design using Tiempo Asynchronous Circuit Compiler (ACC). If you would like to get a "hands-on" understanding of how to do asynchronous design, and where it can be applied, then these workshops are for you.

For managers and executives preferring a broad overview, we will offer high-level presentations as well.

Each presentation/tutorial will run twice per day, and capacity for each session is limited to 8 people. So we highly encourage you to pre-register and reserve your seat in advance.

TUTORIAL 1: Tiempo technology overview – 0h50
Targeted audience	Managers and Executives
Content outline	Principles of Tiempo clockless/asynchronous design technology Features, benefits, applications Case-studies and results to date Tiempo design & verification flow overview

Click here to get the presentation

TUTORIAL 2: Modeling, simulation and debug of clockless circuits with SystemVerilog – 0h50
Targeted audience	Design Engineers, Verification Engineers, and Architects
Content outline	SystemVerilog coding style for clockless design How to model clockless circuits (live demonstration, w/examples) How to simulate, debug, verify clockless circuits (live demonstration, w/examples) Tips, tricks and lessons learned

Click here to get the presentation

TUTORIAL 3: Synthesis and Implementation of clockless circuits – 0h50
Targeted audience	Designers and Architects
Content outline	Overview of Tiempo Asynchronous Circuit Compiler (ACC) How to do synthesis, timing analysis of clockless circuits How to do place & route of clockless circuits How to integrate clockless designs with legacy/clocked designs DFT for clockless circuits Tips, tricks and lessons learned

Click here to get the presentation

TUTORIAL SCHEDULE
	9.30am - 10.20am	11am - 11.50am	2pm - 2.50pm	4pm - 4.50pm
Monday 6th	Tutorial 1	Tutorial 2	Tutorial 3	Tutorial 1
Tuesday 7th	Tutorial 1	Tutorial 2	Tutorial 3	Tutorial 2
Wednesday 8th	Tutorial 1	Tutorial 2	Tutorial 3	Tutorial 3