Cryptoprocessors IP cores: DES

Tiempo DES/3DES IP core offers an unmatched performance over power consumption ratio. Operating at a wide and variable voltage range, this core enable very fast transaction for embedded applications. It is also highly secured against attacks thanks to its asynchronous implementation.

Key benefits

DES Block Diagram
DES Architecture Block Diagram
  • Ultra-low power consumption
  • Ultra-low current peaks
  • Work at low and variable voltage
  • Resistant to power and fault attacks

Key Features

  • FIPS 46-3 Standard Compliant
  • Fast execution of standard ciphering and deciphering algorithms DES, DES-1, 3DES, 3DES-1
  • Fully asynchronous and delay insensitive
  • Available as Verilog netlist[1] ready for P&R (silicon proven netlist)
  • Optional: Verilog netlist[1] secured against hardware attacks
  • Optional: Verilog netlist[1] strengthened for ultra-low noise and ultra low EMI

Applications

Targeted applications are chips for smartcards (with or without contact), RFID, tags, sensor networks, systems embedding NFC technology and other secured applications.

Electrical characteristics

DES4 test chip

Measurements below were performed on the DES4 chip designed and processed in a general-purpose CMOS 130 nm technology.

Supply voltage range 0.6V 1.2V
Max peak-to-peak current
 250µA 800µA
Average current consumption 200µA 1mA
DES execution time 2.3µs 250ns

[1]Please contact Tiempo for available libraries and technologies