Cryptoprocessors IP cores: DES

• Overview
• DES / 3DES
• AES
• RSA & ECC
• Secured hardware design

Tiempo DES/3DES IP core offers an unmatched performance over power consumption ratio. Operating at a wide and variable voltage range, this core enable very fast transaction for embedded applications. It is also highly secured against attacks thanks to its asynchronous implementation.

Key benefits

DES Architecture Block Diagram

• Ultra-low power consumption
• Ultra-low current peaks
• Work at low and variable voltage
• Resistant to power and fault attacks

Key Features

• FIPS 46-3 Standard Compliant
• Fast execution of standard ciphering and deciphering algorithms DES, DES-1, 3DES, 3DES^-1
• Fully asynchronous and delay insensitive
• Available as Verilog netlist^[1] ready for P&R (silicon proven netlist)
• Optional: Verilog netlist^[1] secured against hardware attacks
• Optional: Verilog netlist^[1] strengthened for ultra-low noise and ultra low EMI

Applications

Targeted applications are chips for smartcards (with or without contact), RFID, tags, sensor networks, systems embedding NFC technology and other secured applications.

Electrical characteristics

DES⁴ test chip

Figures below are based on electrical simulation s on TSCM130LP 1.5V process after Place & Route. Simulations are run on the secured version of the IP

^[1]Please contact Tiempo for available libraries and technologies