News
Dec 2011: Tiempo releases FPGA emulator and SDK of TESIC secure platform
Tiempo announces the release of the preliminary version of TESIC, its highly secure, high speed embedde secure platform. This first release is an evaluation kit containing an FPGA-based emulator with a complete SDK for software development.
- Xilinx virtex6 FPGA emulating Tiempo clockless secure platform
- Full SDK tool chain available
- Complete set of software libraries included
- Contact Tiempo for more information
Nov 2011: Tiempo listed in the EE Times 60 Emerging Silicon Startups for the third consecutive year
- For the third consecutive year, Tiempo is listed in the "EE Times 60 Emerging Silicon Startups" list version 12.0.
- View the list on EETimes here (publication to be purchased)
Sep 2011: Tiempo announces the release of ACC, unique synthesis tool for clockless design
Tiempo announces today the release of ACC. After a successful beta-test with Tiempo partners, the first release of our unique synthesis tool for clockless design is now available!
- ACC is an automated synthesis tool for clockless design
- ACC is based on standard language (SV) and operates within standard flows
- Contact Tiempo for more information or visit our web page presenting ACC.
Jun 2011: Tiempo offers free clockless design tutorials at DAC2011
- Tiempo will present free tutorials on clockless design:
- TUTORIAL 1: Tiempo technology overview
- TUTORIAL 2: Modeling, simulation and debug of clockless circuits with SystemVerilog
- TUTORIAL 3: Synthesis and Implementation of clockless circuits
- Space is limited, click here to book your seat and for more details
- Visit Tiempo at booth #3039 at the 48th DAC taking place in San Diego, June 6-8.
- Visit DAC website
Nov 2010: Tiempo listed in the EE Times 60 Emerging Silicon Startups
- Tiempo is listed in the "EE Times 60 Emerging Silicon Startups" list version 11.0.
- View article on EETimes here