Fast wake-up
Tiempo clockless IPs do not need to resume a clock to wake-up, as a result, wake-up time is 1000X shorter than in clocked systems
Yield improvement
Tiempo clockless designs are very robust to on-chip variations: local temperature, voltage or process variations will not affect the correctness of the chip which will increase your yield
Ultra low power
Tiempo clockless IPs allow ultra-low-power design dividing power consumption by a factor 4 to 5 compared to similar clocked circuits
Low noise, low EMI
The current profile of blocks generated with Tiempo clockless technology is very flat, leading to a ultra-low noise and EMI.
Optimal speed
In a clockless circuit, computational blocks are never waiting for a clock edge to proceed to the next step. Tiempo IPs are speed/power consumption optimum
Ease of design
Tiempo IPs are described in standard SystemVerilog language, a simple and straightforward representation for clockless systems
Committed to your success
Tiempo team is committed to the success of your design integrating our IPs. We will engage on performances and ensure your circuit is up and running in a minimum time
Self-adaptive IC
ICs designed using Tiempo clockless technology can natively work with a varying environment (input voltage, temperature) without additional logic traditionally required to do so
Faster time-to-market
By suppressing major design efforts on clock distribution and timing closure issues, Tiempo clockless design methodology allows to significantly accelerate your engineering time
Secured hardware
Traditional hardware attacks such as power analysis and fault injection cannot be easily applied to clockless systems
